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BERT428 100G BERT 誤碼率測試儀

BERT428 100G BERT 誤碼率測試儀

LUCEO BERT428是由速率從2Gbps到28.05Gbps的4通道高速碼型發(fā)生模塊組成及25Gbps到28.05Gbps的4通道誤碼檢測模塊，模塊可以串聯(lián)時鐘工作，因此它是100Gb/s和未來400Gb/s應(yīng)用的理想測試解決方案。

BERT428 is 100Gb/s BERT. EPG428 is an Electrical Pattern Generator module that plugs into the PARALLEX? Chassis. EPG428 can generate 4 channel electrical data from 1 Gb/s up to 29 Gb/s continuously. EED428 is an Electrical Error Detector module that plugs into the PARALLEX? Chassis. EED428 can check 4 channels electrical data from 22.0 - 28.2Gbps and 8.5Gb/s – 14.1Gb/s.

EPG428 Key Spec

PARAMETER SYMBOL VALUE UNIT NOTE
channels chNo 4 ? ?
Data Rate DR 1… 29 Gbps 1)
Data Format ? NRZ ? ?
PRBS Pattern ? 9, 15, 31 ? ?
Differential Data Output Amplitude DOutP/N 200…800 mVpp setting range, 3)
Output Jitter (RMS) Jrms 200 fs Typical, 2)
Single ended Data Output Impedance ZOse 50 W Typical
Data Output Termination ? AC - coupled ? ?
Clock Input / Output Frequency FClk 0.5…14.5 GHz ?
Clock Input / Output Termination ? AC - coupled ? ?

Note:

  1. Output of clock signal is used for daisy chaining additional modules. Maximum daisy chain length is four.
  2. RJ measured with CLK pattern. Depends on applied clock signal (measured with CLK20-2 Module, RJ=200fs)
  3. Measured at 1GBd at the static High/ Low level of the signal with de-emphasis=0dB.
    The eye height at higher data rates might differ.

EED428 Key Spec

PARAMETER SYMBOL Min Max UNIT NOTE
Channels chNo ? 4 ? ?
Data Rate DR 8.5 22.0 14.1 28.2 Gbps 1)
Data Formats ? ????????????????????? NRZ ? ? ?
PRBS Pattern ? 7, 9, 15, 23, 31 ? ? ?
Differential Data Input Amplitude DOutP/N 200 1200 mVpp 3), 4)
Differential Data Input Impedance ZOse 90 110 W ?
Data Input Termination ? AC - coupled ? ? ?
Clock Input / Output Frequency FClk 12.8 14.2 GHz 2)
Clock Input / Output Termination ? AC - coupled ? ? ?

Note:

  1. Apply full rate clock for low data rate range and half rate clock for high data rate range.
  2. Additional DR/40 CLK output installed
  3. BER of better than 1E-12 can only be achieved if at least the min. input voltage level is applied
  4. Minimum input voltage to guarantee error free detection (BER < 10-12) at PRBS31. The input sensitivity of??????????
    the module will be better for input signals with lower bandwidth, e.g. PRBS7.

EPG428

  • Data Rates 1 to 29 Gbps
  • 4 channels
  • Operates with half rate clock
  • Differential Electrical Pattern Generator (K Connector)
  • Reference clock output to drive SERDES, CDR
    that require low speed clock
  • PRBS pattern: 9, 15, 31
  • Data output polarity swap
  • High speed Clock Input and Output
  • GPIB/LAN/USB Interface
    via PARALLEX? Chassis.
  • Small size: width 50.8mm (2”)

EED428

  • Data Rates 22.0 - 28.2Gbps and 8.5Gb/s – 14.1Gb/s Gbps
  • 4 channels
  • Integrated individual CDR on each channel to track incoming data
  • Operates with half rate clock
  • Differential Electrical Error Detector (K Connector)
  • Reference clock output to drive SERDES, CDR
    that require low speed clock
  • PRBS pattern: 7, 9, 15, 23, 31
  • Data input polarity swap
  • BER detection down to 1E-15
  • High speed Clock Input and Output
  • GPIB/LAN/USB Interface via mainframe
  • Small size: width 50.8mm (2”)
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